For a semiconductor power device including, for example, the MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the IGBT (Insulated-Gate Bipolar transistor), and other various types of transistors, it is becoming more and more important to optimize its performance characteristics such as Cgd (capacitance between gate and drain) and breakdown voltage. For example, compared with a trench MOSFET having trenched gates conventionally comprising a single electrode in an active area, a trench MOSFET having shielded gate structure in the active area (as disclosed in prior art of U.S. Pat. No. 7,855,415 shown in FIG. 1A) is more attractive due to its increased breakdown voltage as well as its reduced Cgd in accordance with its reduced charges between gate and drain, making an excellent choice for power switching applications such as inverters and DC to DC power supply circuits. As illustrated in FIG. 1A, the shielded gate structure comprises a shielded electrode in a lower portion and a gate electrode in an upper portion. Furthermore, in order to enhance capability of ESD protection, an ESD clamp diode comprising multiple alternatively arranged n+ doped region and p doped region is usually integrated with a semiconductor power device for example a trench MOSFET having shielded gate structure as discussed above. FIG. 1B shows a semiconductor power device having shielded gate structure and ESD clamp diode disclosed in the same prior art as FIG. 1A where three poly-silicon layers are required in manufacturing process respectively for: the shielded electrode, the gate electrode and the ESD clamp diode, at the same time, according to the prior art, another two masks are needed to respectively define the area for the trenched gates having shielded gate structure and for the ESD clamp diode. However, when it is more and more important to reduce the manufacturing cost for semiconductor power devices, all the poly-silicon layers and the masks needed in the prior art are not cost effective for mass production.
Therefore, there is still a need in the art of the semiconductor power device design and fabrication, particular for the semiconductor power device having shielded gate structure integrated and an ESD clamp diode, to provide a novel cell structure, device configuration and fabrication process that would further reduce the number of masks and poly-silicon layers applied in the manufacturing process for cost reduction without sacrificing any performance of the semiconductor power device.